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Solutions

The Verification Academy Solutions section delivers focused insights into key market segments and verification products that address today’s emerging challenges. Explore how advanced technologies and methodologies—spanning functional verification, safety, security, and more—are applied to solve real-world design problems. This curated content brings together best practices, expert perspectives, and proven tools to accelerate verification success.
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Unified Coverage

Design for Test Verification

Accelerating DFT Sign-Off with Questa One

Tackling Emerging DFT Verification Challenges with Questa One

Functional Safety

Functional Safety for ISO 26262

Functional Safety for DO-254

Unified Coverage

Questa One Unified Coverage Solution: Transforming Verification Through Intelligence

Boost Your Verification Productivity with Questa Verification IQ

Coverage Closure Acceleration Using Collaborative Verification IQ Tool

Functional Safety for ISO 26262

Accelerated Assurance with Questa One Functional Safety

Functional Safety for DO-254

Introduction to DO-254
Topics

The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
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Clock-Domain Crossing

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Reset-Domain Crossing

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Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
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Verification Horizons Blog

From Rule-Based Beginnings to AI-Driven Design: Tracing the Evolution of AI in EDA

DFT Verification: Tackling the Evolving Challenges

Closing the Gap in Software Skills for Verification Engineers

Accellera announces fee-free availability of IEEE Std. 1801™-2024

Got Coverage?

Update from the Standards World: Accellera Approves UVM-MS 1.0 Standard

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Siemens EDA at DAC 2025

Siemens at Paris Air Show 2025

Verification Futures Conference 2025 UK

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Library Archive

Coverage

Accelerating Functional Coverage with Questa One CX

Simulation

Tackling Emerging DFT Verification Challenges with Questa One

Debug

Faster Debug of Complex Testbenches using Visualizer

Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

Prevent Performance Problems with Prompt RTL Profiling

Accelerate Development Using Advanced Debugging Approaches

Formal Verification

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Explore How to Protect Against Data Corruption with Formal Security Verification

Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs

Functional Verification Workflow for Trusted and Assured Microelectronics

FPGA Verification

Securing your FPGA Design from RTL through to the Bitstream

Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream

Bringing Model-based Systems Engineering to IC and FPGA Design

ModelSim to Questa - Productivity Features

Functional Safety

Enhancing Automotive Safety Verification Using Questa One Sim FX

Enhancing Defect Coverage in DFT

Safety Analysis for Automotive Chips Based on ISO 26262

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Union of SoC Design & Functional Safety FlowUnion of SoC Design & Functional Safety Flow

Questa Design Solutions

Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Continuous Integration (CI) Driving Efficient Program Execution

Questa Design Solutions as a Sleep Aid

Applying Machine Learning to Accelerate CDC Analysis

Formal and the Next Normal

Questa Lint vs Formal AutoCheck

SystemVerilog

Introduction to SystemVerilog Assertions

Easy Test Writing with a Proxy-driven Testbench

Making Your DPI-C Interface a Fast River of Data

The Life of a SystemVerilog Variable

Verification IP

Breaking Barriers: Ethernet 1.6T, Infiniband, UALink, and UEC Verification for Next-Gen Connectivity

PCIe Gen7 Verification with Siemens Avery Verification IP

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

The Future of Multi-Die System Verification with UCIe

Verification IQ

Streamlining Requirements Traceability using Questa Verification IQ Testplan Author

Smart Debug: Accelerate Root Cause Analysis and Reduce Debug Turnaround Time with Questa Verification IQ Regression Navigator

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

Boost Your Verification Productivity with Questa Verification IQ

Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data

Verification Planning

Solving the Semiconductor Verification Crisis: From Problem to Productivity

Functional Verification Study - 2022

The Three Pillars of Intent-Focused Insight

Trends in Functional Verification

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September 2024

MARLUG - 2024
FPGA Verification Sep 18, 2024 Austin Mam Seminar

October 2023

MARLUG - 2023
Machine Learning Oct 30, 2023 Harry Foster Seminar

March 2021

Early Design & Validation of an AI Accelerator’s Performance Using an HLS Design
High-Level Synthesis Mar 31, 2021 Michael Fingeroff - Siemens Eda Seminar

February 2011

SystemVerilog Concurrent Assertions
SystemVerilog Feb 25, 2011 Cliff Cummings Seminar

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